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HT32F52220/ht32f52230 datasheet 32-bit arm ? cortex?-m0+ microcontroller, up to 32 kb flash and 4 kb sram with 1 msps adc, usart, uart, spi, i 2 c, gptm, sctm, bftm, wdt revision: v1.21 date: april 11, 2017
rev. 1.21 2 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 table of contents table of contents 1 general description ........... ..................................................................................... 6 2 features ................................................................................................................... 7 core ....................................................................................................................................... 7 on-chip memory .................................................................................................................... 7 flash memory controller C fmc ............ ................................................................................ 7 reset control unit C rstcu ................................................................................................. 8 clock control unit C ckcu ............ ........................................................................................ 8 power management C pwrcu ............................................................................................. 8 external interrupt/event controller C exti ............................................................................ 9 analog to digital converter C adc ........................................................................................ 9 i/o ports C gpio .................................................................................................................... 9 pwm generation and capture timers C gptm .................................................................. 10 single channel generation and capture timers C sctm ................................................... 10 basic function timer C bftm ............................................................................................. 10 watchdog timer C wdt ....................................................................................................... 11 inter-integrated circuit C i 2 c ................................................................................................ 11 serial peripheral interface C spi ......................................................................................... 12 universal synchronous asynchronous receiver transmitter C usart .............................. 12 universal asynchronous receiver transmitter C uart ...................................................... 13 debug support ..................................................................................................................... 13 package and operation temperature .................................................................................. 13 3 overview ................................................................................................................ 14 device information ............................................................................................................... 14 block diagram ..................................................................................................................... 15 memory map ........................................................................................................................ 16 clock structure ........... ......................................................................................................... 18 4 pin assignment ..................................................................................................... 19 5 electrical characteristics ..................................................................................... 24 absolute maximum ratings ................................................................................................. 24 recommended dc operating conditions ........................................................................... 24 on-chip ldo voltage regulator characteristics ................................................................. 24
rev. 1.21 3 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 table of contents table of contents power consumption ............................................................................................................ 25 reset and supply monitor characteristics ........................................................................... 26 external clock characteristics ............................................................................................. 27 internal clock characteristics .............................................................................................. 28 pll characteristics .............................................................................................................. 28 memory characteristics ....................................................................................................... 28 i/o port characteristics ........................................................................................................ 29 adc characteristics ........... ................................................................................................. 30 sctm/gptm characteristics .............................................................................................. 31 i 2 c characteristics ............................................................................................................... 32 spi characteristics ........... ................................................................................................... 33 6 package information ............................................................................................ 35 24-pin ssop (150mil) outline dimensions ............ .............................................................. 36 28-pin ssop (150mil) outline dimensions ............ .............................................................. 37 saw type 33-pin (4mm4mm) qfn outline dimensions ................................................... 38
rev. 1.21 4 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 list of tables list of tables table 1 features and peripheral list ...... ................................................................................................. 14 table 2 register map .............................................................................................................................. 17 table 3 series pin assignment for 33-pin qfn, 24/28-pin ssop package ...... ...................................... 22 table 4 pin description ...... ...................................................................................................................... 23 table 5 absolute maximum ratings ......................................................................................................... 24 table 6 recommended dc operating conditions ................................................................................... 24 table 7 ldo characteristics ...... .............................................................................................................. 24 table 8 power consumption characteristics ........................................................................................... 25 table 9 v dd power reset characteristics ................................................................................................ 26 table 10 lvd/bod characteristics .......................................................................................................... 26 table 11 high speed external clock (hse) characteristics .................................................................... 27 table 12 high speed internal clock (hsi) characteristics ...................................................................... 28 table 13 low speed internal clock (lsi) characteristics ........................................................................ 28 table 14 pll characteristics ................................................................................................................... 28 table 15 flash memory characteristics ................................................................................................... 28 table 16 i/o port characteristics ............................................................................................................. 29 table 17 adc characteristics .................................................................................................................. 30 table 18 sctm/gptm characteristics .................................................................................................... 31 table 19 i 2 c characteristics ..................................................................................................................... 32 table 20 spi characteristics .................................................................................................................... 33
rev. 1.21 5 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 list of tables list of figures list of figures figure 1 block diagram ........................................................................................................................... 15 figure 2 memory map .............................................................................................................................. 16 figure 3 clock structure .......................................................................................................................... 18 figure 4 24-pin ssop pin assignment .................................................................................................... 19 figure 5 28-pin ssop pin assignment .................................................................................................... 20 figure 6 33-pin qfn pin assignment ...................................................................................................... 21 figure 7 adc sampling network model .................................................................................................. 31 figure 8 i 2 c timing diagrams ....... ........................................................................................................... 32 figure 9 spi timing diagrams C spi master mode ................................................................................. 34 figure 10 spi timing diagrams C spi slave mode with cpha=1 ....... .................................................... 34
rev. 1.21 6 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 general description 1 general description the holtek HT32F52220/52230 devices are high performance , low power consumption 32-bit microcontroller s based around a n arm ? cor tex?-m 0+ processor core. the cortex?-m 0+ is a next - generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer , and including advanced debug support. the devices operate at a frequency of up to 40 mhz for HT32F52220/52230 with a flash accelerator to obtain maximum effciency. it provides up to 32 kb of embedded flash memory for code/data storage and 4 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, u s art, uart, s pi , gptm, sctm, bftm, wdt, sw-dp (serial wire debug port) , etc. , are also implemented in th e device series . several power saving modes provide the fexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the device s are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitor s, alarm systems, consumer products, handheld equipment, data logging applications , motor control and so on.
rev. 1.21 7 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 general description features 2 features core 32-bit arm ? cortex?-m0+ processor core up to 40 mhz operati ng frequency 0.93 dmips/mhz (dhrystone v2.1) single-cycle multiplication integrated nested vectored interrupt controller (nvic) 24-bit systick timer the cortex?-m0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized, low-power processor. the processor is based on the armv6-m architecture and supports thumb ? instruction sets; single-cycle i/o port; hardware multiplier and low latency interrupt respond time. on-chip memory up to 32 kb on-chip flash memory for instruction/data and options storage 4 kb on-chip sram supports multiple boot modes the arm ? cortex?-m0+ processor accesses and debug accesses share the single external interface to external ahb peripherals. the processor accesses take priority over debug accesses. the maximum address range of the cortex?-m0+ is 4 gb since it has a 32-bit bus address width. additionally, a pre-defined memory map is provided by the cortex?-m0+ processor to reduce the software complexity of repeated implementation by different device vendors. however, some regions are used by the arm ? cortex?-m0+ system peripherals. refer to the arm ? cortex?-m0+ technical reference manual for more information. figure 2 shows the memory map of the ht32f522320/52230 series of devices, including code, sram, peripheral, and other suhghqhguhlrqv flash memory controller C fmc 32-bit word programming with in system programming interface (isp) and in application programming (iap) flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory word program/page erase functions are also provided.
rev. 1.21 8 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features reset control unit C rstcu supply supervisor: power on reset / power down reset C por/pdr brown-out detector C bod programmable low voltage detector C lvd the reset control unit , rstcu , has three kinds of reset, a power on reset, a system reset and an apb unit reset. the power on reset, known as a cold reset, resets the full system during power up. a system reset resets the processor core and peripheral ip components with the exception of the sw-dp controller. the resets can be triggered by an external signal, internal events and the reset generators. clock control unit C ckcu external 4 to 16 mhz crystal oscillator internal 8 mhz rc oscillator trimmed to 2 % accuracy at 3.3v operating voltage and 25c operating temperature internal 32 khz rc oscillator integrated system clock pll independent clock divider and gating bits for peripheral clock sources the clock control unit, ckcu, provides a range of oscillator and clock functions. these include a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a phase lock loop (pll), a hse clock monitor, clock prescalers, clock multiplexers, apb clock divider and gating circuitry. the ahb, apb and cortex tm -m0+ clocks are derived from the system clock (ck_sys) which can come from the hsi, hse or pll. the watchdog timer and real time clock (rtc) use the lsi as their clock source. power management C pwrcu single v dd power supply: 2.0 v to 3.6 v integrated 1.5 v ldo regulator for cpu core, peripherals and memories power supply two power domains: v dd , 1.5 v. four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down power consumption can be regarded as one of the most important issues for many embedded system applications. accordingly the power control unit, pwrcu, in these devices provides many types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best wudghriiehwhhqwkhfrqlfwlqghpdqgvri38rshudwlqwlphvshhgdqgsrhufrqvxpswlrq
rev. 1.21 9 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features features external interrupt/event controller C exti all gpio pins can be selected as exti trigger source source trigger type includes high level, low level, negative edge, positive edge, or both edge individual interrupt enable, wakeup enable and status bits for each exti line software interrupt trigger mode for each exti line the external interrupt/event controller, exti, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. each exti line can also be masked independently. analog to digital converter C adc 12-bit sar adc engine up to 1 msps conversion rate up to 8 external analog input channels a 12-bit multi-channel adc is integrated in the device. there are multiplexed channels, which include 8 external analog signal channels and 2 internal channels which can be measured. if the input voltage is required to remain within a specific threshold window, an analog watchdog function will monitor and detect the se signal s . an interrupt will then be generated to inform the device that the input voltage is not within the pre set threshold level s. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. i/o ports C gpio up to 23 gpios port a, b are mapped as 16 external interrupts C exti there are up to 23 general purpose i/o pins, gpio, named port a and port b for the implementation of logic input/output functions. each of the gpio ports has a series of related frqwurodqgfrqxudwlrquhlvwhuvwrpdlplh hlelolwdqgwrphhw the requirements of a wide range of applications. the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by configuring the corresponding registers regardless of the input or output pins. the external lqwhuuxswvrqwkh3,2slqvriwkhghylfhkdyhuhodwhgfrqwurodqgfrqxudwlrquhlvwhuvlqwkh external interrupt control unit , exti.
rev. 1.21 10 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features pwm generation and capture timers C gptm one 16-bit up, down, up/down auto-reload counter 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 input capture function compare match output pwm waveform generation with edge-aligned and center-aligned counting modes single pulse mode output encoder interface controller with two inputs using quadrature decoder the general purpose timer consists of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement , input signal pulse width measurement , output waveform generation such as single pulse generation , or pwm output generation . the gptm supports an encoder interface using a decoder with two inputs. single channel generation and capture timers C sctm one 16-bit up and auto-reload counter one channel for each timer 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536 input capture function compare match output pwm waveform generation with edge-aligned single pulse mode output the single-channel timer consists of one 16-bit up-counter, one 16-bit capture/compare register (ccr), one 16-bit counter-reload register (crr) and several control/status registers. it can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or pwm output. basic function timer C bftm one 32-bit compare/match count-up counter C no i/o control features one shot mode C counting stops after a match condition repetitive mode C restart counter after a match condition the basic function timer is a simple count- up 32-bit counter designed to measure time interval s and generate a one shot or repetitive interrupt s . the bftm operates in two functional modes, repetitive or one shot mode. in the repetitive mode the bftm restarts the counter when a compare match event occurs. the bftm also supports a o ne shot mode which forces the counter to stop counting when a compare match event occurs.
rev. 1.21 11 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features features watchdog timer C wdt 12-bit down counter with 3-bit prescaler reset event for the system programmable watchdog timer window function register write protection function the watchdog timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. it includes a 12-bit count- down counter, a prescaler, a wdt delta value register, wdt operation control circuitry and a wdt protection mechanism. if the software does not reload the counter value before a :dwfkgr7lphuxqghurrffxuvduhvhwlooehhqhudwhg when the counter underflows. in addition, a reset is also generated if the software reloads the counter when the counter value is greater than the wdt delta value. this means the counter must ehuhordghglwklqdolplwhgwlplqlqgrxvlqdvshflfphwkrg7kh:dwfkgr7lphufrxqwhu can be stopped while the processor is in the debug mode. there is a register write protect function which can be enabled to prevent it from changing the watchdog timer frqxudwlrq unexpectedly. inter-integrated circuit C i 2 c supports both master and slave modes with a frequency of up to 1 mhz provide an arbitration function and clock synchronization supports 7-bit and 10-bit addressing mode s and general call addressing supports slave multi-addressing mode with maskable address the i 2 c is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: (1) 100 khz in the standard mode, (2) 400 khz in the fast mode and (3) 1 mhz in the fast plus mode . the scl period generation register is used to setup different kinds of duty cycle implementation s for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c also has an arbitration detect function and clock synchronization to prevent situation s where more than one master attempts to transmit data to the i 2 c bus at the same time.
rev. 1.21 12 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features serial peripheral interface C spi supports both master and slave mode frequency of up to (f pclk /2) mhz for the master mode and (f pclk /3) mhz for the slave mode fifo depth: 8 levels multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and output lines miso and mosi, the clock line, sck, and the slave select line, sel. one spi device acts as a master device klfkfrqwurovwkhgdwdrxvlqwkh6(/dqg6.vlqdovwrlqglfdwhwkh start of data communication and the data sampling rate. to receive a data byte, the streamed data elwvduhodwfkhgrqdvshflfforfnhghdqgvwruhglqwkhgdwduhlvwhurulqwkh5;),)2dwd transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications. universal synchronous asynchronous receiver transmitter C usart supports both asynchronous and clocked synchronous serial communication modes asynchronous operating baud rate up to (f pclk /16) mhz and synchronous operating rate up to (f pclk /8) mhz full duplex communication fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lwrughu/6%uvwru06%uvwwudqvihu error detection: parity, overrun and frame error C rts, cts irda sir encoder and decoder rs485 mode with output enable control fifo depth: 8 9 bits for both receiver and transmitter 7kh8qlyhuvdo6qfkurqrxvvqfkurqrxv5hfhlyhu7udqvfhlyhu8657surylghvdhleohixoo duplex data exchange using synchronous or asynchronous data transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the usart module includes a transmitter fifo, (tx_fifo) and receiver fifo (rx_fifo). the s oftware can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events.
rev. 1.21 13 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 features features universal asynchronous receiver transmitter C uart asynchronous serial communication operating baud-rate up to (f pclk /16) mhz full duplex communication fully programmable serial communication characteristics including: word length: 7, 8, or 9-bit character parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lwrughu/6%uvwru06%uvwwudqvihu error detection: parity, overrun and frame error the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports line status interrupt. the s oftware can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions resulting from parity, overrun, framing and break events. debug support serial wire debug port C sw-dp 4 comparators for hardware breakpoint or code / literal patch 2 comparators for hardware watchpoints package and operation temperature 24/28-pin ssop, 33-pin qfn package operation temperature range: -40c to +85c
rev. 1.21 14 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview 3 overview device information table 1 features and peripheral list peripherals HT32F52220 ht32f52230 main flash (kb) 16 31 option bytes flash (kb) 1 1 sram (kb) 4 4 timers gptm 1 sctm 2 bftm 1 wdt 1 communication spi 1 usart 1 uart 1 i 2 c 1 exti 16 12-bit adc number of channels 1 8 channels gpio up to 23 cpu frequency up to 40 mhz operating voltage 2.0 v ~ 3.6 v operating temperature -40c ~ +85c package 24/28-pin ssop, 33-pin qfn
rev. 1.21 15 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview overview block diagram sw-dp apb ahb peripherals flash memory cortex tm -m0+ processor system nvic sram controller fmc control registers ckcu/rstcu control registers interrupt request usart afio exti ch3 ~ ch0 boot clock and reset control power control bus matrix af af af af powered by v dd15 swclk swdio sda scl af power supply: bus: control signal: alternate function: af powered by v dd15 mosi, miso sck, sel af flash memory interface tx, rx rts/txe cts/sck lsi 32 khz v dd v ss pwrcu nrst wakeup af powered by v dda v dda v ssa adc_in0 ... adc_in7 af i2c adc 12-bit sar adc bftm ahb to apb bridge wdt gpio pa; pb af tx, rx io port uart spi powered by v dd v ss v dd por /pdr bod lvd xtalin xtalout hsi 8 mhz hse 4 ~ 16 mhz af ldo 1.5 v gptm cldo cap. powered by v dd sctm0 ~ 1 sctm0 ~ sctm1 af pll sram figure 1 block diagram
rev. 1.21 16 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview memory map reserved reserved reserved gpio a b reserved reserved reserved bftm gptm pwrcu reserved reserved reserved reserved reserved reserved 0x4002_2000 reserved up to 32 kb on-chip flash 0x0000_0000 reserved 0x000_8000 boot loader 0x1f00_0000 reserved 0x1f00_0800 option byte alias 0x1ff0_0000 up to 32 kb 2 kb 1 kb reserved 0x1ff0_0400 code sram peripheral 4 kb on-chip sram 0x2000_0000 reserved 0x2000_1000 4 kb apb peripherals 0x4000_0000 ahb peripherals 0x4008_0000 0x4010_0000 private peripheral bus 0xe000_0000 reserved 0xe010_0000 0xffff_ffff 512 kb 512 kb usart 0x4000_0000 uart 0x4000_1000 spi 0x4000_4000 0x4000_5000 i2c adc reserved 0x4001_0000 exti 0x4002_3000 afio 0x4002_4000 wdt 0x4003_5000 0x4004_8000 0x4006_9000 0x4006_b000 0x4006_a000 0x4004_9000 0x4006_e000 0x4003_4000 apb fmc 0x4008_0000 reserved 0x4008_2000 ckcu/rstcu 0x4008_8000 0x400f_ffff ahb 0x4000_2000 0x4002_5000 0x4008_a000 0x400b_0000 0x400b_4000 0x4001_1000 0x4006_8000 0x4006_f000 0x4007_6000 0x4007_7000 sctm0 sctm1 0x4007_4000 reserved 0x4007_5000 figure 2 memory map
rev. 1.21 17 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview overview table 2 register map start address end address peripheral bus 0x4000_0000 0x4000_0fff usart apb 0x4000_1000 0x4000_1fff uart 0x4000_2000 0x4000_3fff reserved 0x4000_4000 0x4000_4fff spi 0x4000_5000 0x4001_9fff reserved 0x4001_0000 0x4001_0fff adc 0x4001_1000 0x4002_1fff reserved 0x4002_2000 0x4002_2fff afio 0x4002_3000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff exti 0x4002_5000 0x4003_3fff reserved 0x4003_4000 0x4003_4fff sctm0 0x4003_5000 0x4004_7fff reserved 0x4004_8000 0x4004_8fff i 2 c 0x4004_9000 0x4006_7fff reserved 0x4006_8000 0x4006_8fff wdt 0x4006_9000 0x4006_9fff reserved 0x4006_a000 0x4006_afff rtc/pwrcu 0x4006_b000 0x4006_dfff reserved 0x4006_e000 0x4006_efff gptm 0x4006_f000 0x4007_3fff reserved 0x4007_4000 0x4007_4fff sctm1 0x4007_5000 0x4007_5fff reserved 0x4007_6000 0x4007_6fff bftm 0x4007_7000 0x4007_ffff reserved 0x4008_0000 0x4008_1fff fmc ahb 0x4008_2000 0x4008_7fff reserved 0x4008_8000 0x4008_9fff ckcu/rstcu 0x4008_a000 0x400a_ffff reserved 0x400b_0000 0x400b_1fff gpioa 0x400b_2000 0x400b_3fff gpiob 0x400b_4000 0x400f_ffff reserved
rev. 1.21 18 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview clock structure 4-16 mhz hse xtal 8 mhz hsi rc 32 khz lsi rc legend: hse = high speed external clock hsi = high speed internal clock lsi = low speed internal clock wdtsrc pllsrc ahb prescaler 1,2,4,8,16,32 fclk ( free running clock) stclk (to systick) ck_adc ip ck_wdt wdten ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[2:0] hseen hsien lsien f ck_sys,max = 40 mhz ck_lsi reserved ck_ahb/16 ck_hsi ck_hse pclk ( afio, adc, spi, usart, uart, i2c, gptm, sctmx, bftm, exti, wdt) pll clock monitor pllen ck_pll adcen f ck_pll,max = 40 mhz (recommended) ck_lsi hclks ( to sram) hclkf ( to flash) cm0pen fmcen sramen 1 0 1 0 ck_ahb 000 001 010 011 100 101 110 ck_sys sw[2:0] 00x 011 010 111 110 8 hclkc ( to cortex tm -m0+) cm0pen (control by hw) prescaler 1 ~ 32 ck_ref divider ckrefpre hclkbm ( to bus matrix) bmen hclkapb ( to apb bridge) apben peripherals clock prescaler 1,2,4,8 adc prescaler 1,2,3,4,8... 00 01 10 11 pclk pclk/2 pclk/4 pclk/8 spien extien ck_gpio ( to gpio port) gpioben gpioaen ckrefen cm0pen cm0pen cm0pen reserved figure 3 clock structure
rev. 1.21 19 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 overview pin assignment 4 pin assignment 1 2 3 4 5 6 7 8 9 pb7 pb8 vdda pa0 pa1 pa2 pa3 pa4 pa5 cldo af0 (default) 33v 33v 33v 33v 33v 33v HT32F52220/ht32f52230 24 ssop-a 10 af0 (default) 33v af1 33v ap 11 vdd vss 12 p15 p33 p33 p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad pb4 pb3 pb2 pb1 pb0 pa9_boot xtalout xtalin swclk pa12 pa13 33v 33v 33v 33v 33v 33v 33v 33v 23 22 21 20 19 18 17 16 15 24 pb12 nrst 33v 33v 14 13 33v 33v pb13 pb14 swdio figure 4 24-pin ssop pin assignment
rev. 1.21 20 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 pin assignment 1 2 3 4 5 6 7 8 9 10 11 pb7 pb8 vdda pa0 pa1 pa2 pa3 pa4 pa5 pa7 cldo pb4 pb3 pb2 pb1 pb0 pa15 pa9_boot xtalout xtalin af0 (default) 33v 33v 33v 33v 33v 33v HT32F52220/ht32f52230 28 ssop-a 12 af0 (default) 33v pa6 33v swclk swdio pa12 pa13 af1 pa14 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 27 26 25 24 23 22 21 20 19 18 17 28 ap 13 vdd vss 14 33v p15 p33 p33 pb12 nrst 33v 33v 16 15 33v 33v p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital & analog io pad 3.3 v digital i/o pad pb13 pb14 figure 5 28-pin ssop pin assignment
rev. 1.21 21 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 pin assignment pin assignment vssa n.c. vdda pb8 pb7 pb4 pb2 pb3 32 31 30 29 28 27 26 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 pb1 pb0 pa15 pa14 pa9_ boot xtalin af0 (default) af0 (default) af0 (default) vdd vss nrst n.c. n.c. pb12 p33 vdd 33v vdd 33v vdd 33v vdd 33v p15 33v ap ap HT32F52220/ht32f52230 33 qfn-a 25 cldo af0 (default) p33 33v 33v 33v 33v swclk swdio pa12 pa13 pb13 af1 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 17 xtalout pb14 33v 3.3 v digital & analog io pad p33 ap p15 33v 33v 3.3 v digital power pad 3.3 v analog power pad 1.5 v power pad 3.3 v digital i/o pad vdd vdd domain pad 33 vss 1 2 3 4 5 6 7 8 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 33v 33v 33v 33v 33v 33v 33v 33v figure 6 33-pin qfn pin assignment
rev. 1.21 22 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 pin assignment table 3 series pin assignment for 33-pin qfn, 24/28-pin ssop package package alternate function mapping af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 33qfn 28ssop 24ssop system default gpio adc n/a gptm spi usart /uart i2c n/a n/a n/a n/a n/a sctm n/a system other 1 4 4 pa0 adc_in0 gt_ch0 spi_sck usr_ rts i2c_scl 2 5 5 pa1 adc_in1 gt_ch1 spi_mosi usr_ cts i2c_sda 3 6 6 pa2 adc_in2 gt_ch2 spi_miso usr_tx 4 7 7 pa3 adc_in3 gt_ch3 spi_sel usr_rx 5 8 8 pa4 adc_in4 gt_ch0 spi_sck ur_tx i2c_scl 6 9 9 pa5 adc_in5 gt_ch1 spi_mosi ur_rx i2c_sda 7 10 pa6 adc_in6 gt_ch2 spi_miso 8 11 pa7 adc_in7 gt_ch3 spi_sel 9 12 10 cldo 10 13 11 vdd 11 14 12 vss 12 15 13 nrst 13 n.c. 14 n.c. 15 16 14 pb12 spi_miso ur_rx sctm0 wakeup 16 17 15 xtalin pb13 ur_tx i2c_scl 17 18 16 xtalout pb14 ur_rx i2c_sda 18 19 17 pa9_boot spi_mosi sctm1 19 20 18 swclk pa12 20 21 19 swdio pa13 21 22 pa14 gt_ch0 spi_sel usr_ rts i2c_scl ckout 22 23 pa15 gt_ch0 spi_sck usr_ cts i2c_sda sctm1 23 24 20 pb0 gt_ch1 spi_mosi usr_tx i2c_scl 24 25 21 pb1 gt_ch1 spi_miso usr_rx i2c_sda sctm0 25 26 22 pb2 gt_ch2 spi_sel ur_tx 26 27 23 pb3 gt_ch2 spi_sck ur_rx sctm1 27 28 24 pb4 spi_mosi ur_tx sctm0 28 n.c. 29 1 1 pb7 gt_ch3 spi_miso ur_tx i2c_scl 30 2 2 pb8 gt_ch3 spi_sel ur_rx i2c_sda 31 3 3 vdda 32 vssa 33 vss
rev. 1.21 23 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 pin assignment pin assignment table 4 pin description pin number pin name type (note1) io structure (note2) output driving description 33qfn 28ssop 24ssop default function (af0) 29 1 1 pb7 ai/o 33v 4/8/12/16 ma pb7 30 2 2 pb8 ai/o 33v 4/8/12/16 ma pb8 31 3 3 vdda p analog voltage for adc 32 vssa p analog ground for adc 33 vss p ground reference for digital i/o 1 4 4 pa0 ai/o 33v 4/8/12/16 ma pa0 2 5 5 pa1 ai/o 33v 4/8/12/16 ma pa1 3 6 6 pa2 ai/o 33v 4/8/12/16 ma pa2 4 7 7 pa3 ai/o 33v 4/8/12/16 ma pa3 5 8 8 pa4 ai/o 33v 4/8/12/16 ma pa4 6 9 9 pa5 ai/o 33v 4/8/12/16 ma pa5 7 10 pa6 ai/o 33v 4/8/12/16 ma pa6 8 11 pa7 ai/o 33v 4/8/12/16 ma pa7 9 12 10 cldo p core power ldo 1.5 v output it is recommended to connect a 1 f to 2.2 f capacitor as close as possible between this pin and vss pin. 10 13 11 vdd p voltage for digital i/o 11 14 12 vss p ground reference for digital i/o 12 15 13 nrst note 3 i (v dd ) 33v_pu external reset pin and external wakeup pin in the power- down mode 13 n.c. 14 n.c. 15 16 14 pb12 note 3 i/o (v dd ) 33v 4/8/12/16 ma pb12 16 17 15 pb13 ai/o 33v 4/8/12/16 ma xtalin 17 18 16 pb14 ai/o 33v 4/8/12/16 ma xtalout 18 19 17 pa9 i/o 33v_pu 4/8/12/16 ma pa9_boot 19 20 18 pa12 i/o 33v_pu 4/8/12/16 ma swclk 20 21 19 pa13 i/o 33v_pu 4/8/12/16 ma swdio 21 22 pa14 i/o 33v 4/8/12/16 ma pa14 22 23 pa15 i/o 33v 4/8/12/16 ma pa15 23 24 20 pb0 i/o 33v 4/8/12/16 ma pb0 24 25 21 pb1 i/o 33v 4/8/12/16 ma pb1 25 26 22 pb2 i/o 33v 4/8/12/16 ma pb2 26 27 23 pb3 i/o 33v 4/8/12/16 ma pb3 27 28 24 pb4 i/o 33v 4/8/12/16 ma pb4 28 n.c. note: 1. i = input, o = output, a = analog port, p = power supply, pu = pull-up, v dd = v dd power 2. 33v = 3.3 v tolerant. 3. these pins are located at the v dd power domain.
rev. 1.21 24 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics 5 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. s tresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 5 absolute maximum ratings symbol parameter min max unit v dd external main supply voltage v ss - 0.3 v ss + 3.6 v v dda external analog supply voltage v ssa - 0.3 v ssa + 3.6 v v in input voltage on i/o v ss - 0.3 v ss + 0.3 v t a ambient operating temperature range -40 +85 c t stg storage temperature range -55 +150 c t j maximum junction temperature 125 c p d total power dissipation 500 mw v esd electrostatic discharge voltage C human body mode -4000 +4000 v recommended dc operating conditions table 6 recommended dc operating conditions t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd i/o o perating voltage 2.0 3.3 3.6 v v dda analog operating voltage 2.5 3.3 3.6 v on-chip ldo voltage regulator characteristics table 7 ldo characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v ldo internal regulator output voltage v dd 2.0 v regulator input @ i ldo = 35 ma and voltage vari - ant = 5 %, after trimming. 1.425 1.5 1.57 v i ldo output current v dd = 2.0 v regulator input @ v ldo = 1.5 v 30 35 ma c ldo external filter capacitor value for internal core power supply the capacitor value is depen - dent on the core power cur - rent consumption 1 f
rev. 1.21 25 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics electrical characteristics power consumption table 8 power consumption characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i dd supply current (run mode) v dd = 3.3 v, hse = 8 mhz, pll = 40 mhz, f hclk = 40 mhz, f pclk = 40 mhz, all peripherals enabled 10.5 ma v dd = 3.3 v, hse = 8 mhz, pll = 40 mhz, f hclk = 40 mhz, f pclk = 40 mhz, all peripherals disabled 6.8 ma v dd = 3.3 v, hse off, pll off, lsi on, f hclk = 32 khz, f pclk = 32 khz, all peripherals enabled 44 a v dd = 3.3 v, hse off, pll off, lsi on, f hclk = 32 khz, f pclk = 32 khz, all peripherals disabled 41 a supply current (sleep mode) v dd = 3.3 v, hse = 8 mhz, pll = 40 mhz, f hclk = 0 mhz, f pclk = 40 mhz, all peripherals enabled 5.8 ma v dd = 3.3 v, hse = 8 mhz, pll = 40 mhz, f hclk = 0 mhz, f pclk = 40 mhz, all peripherals disabled 2.0 ma supply current (deep-sleep1 mode) v dd = 3.3 v, all clock off (hse/pll/f hclk ), ldo in low power mode, lsi on 34 a supply current (deep-sleep2 mode) v dd = 3.3 v, all clock off (hse/pll/f hclk ), ldo off dmos on, lsi on. 4.8 a supply current (power-down mode) v dd = 3.3 v, ldo off, dmos off, lsi on. 1.3 a note: 1. hse means high speed external oscillator. hsi means 8 mhz high speed internal oscillator. 2. code = while (1) { 208 nop } executed in flash.
rev. 1.21 26 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics reset and supply monitor characteristics table 9 v dd power reset characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v por power on reset threshold (rising voltage on v dd ) t a = -40c ~ +85c 1.66 1.79 1.90 v v pdr power down reset threshold (falling voltage on v dd ) 1.49 1.64 1.78 v v porhyst por hysteresis 150 mv t por reset delay time v dd = 3.3 v 0.1 0.2 ms note: 1. data based on characterization results only, not tested in production. 2. guaranteed by design, not tested in production. 3. if the ldo is turned on, the vdd por has to be in the de-assertion condition. when the vdd por is in the assertion state then the ldo will be turned off. table 10 lvd/bod characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v bod voltage of brown out detection t a = -40c ~ 85c after factory-trimmed (v dd falling edge) 2.02 2.1 2.18 v v lvd voltage of low voltage detection t a = -40c ~ 85c (v dd falling edge) lvds = 000 2.17 2.25 2.33 v lvds = 001 2.32 2.4 2.48 v lvds = 010 2.47 2.55 2.63 v lvds = 011 2.62 2.7 2.78 v lvds = 100 2.77 2.85 2.93 v lvds = 101 2.92 3.0 3.08 v lvds = 110 3.07 3.15 3.23 v lvds = 111 3.22 3.3 3.38 v v lvdhtst lvd hysteresis v dd = 3.3 v 100 mv t sulvd lvd setup time v dd = 3.3 v 5 s t atlvd lvd active delay time v dd = 3.3 v s i ddlvd operation current note3 v dd = 3.3 v 5 15 a note: 1. data based on characterization results only, not tested in production. 2. guaranteed by design, not tested in production. 3. bandgap current is not included. 4. lvds feld is in the pwrcu lvdcsr register
rev. 1.21 27 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics electrical characteristics external clock characteristics table 11 high speed external clock (hse) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd operation range 2.0 3.6 v f hse high speed external oscillator frequency (hse) 4 16 mhz c lhse load capacitance v dd = 3.3 v, r esr = 100 @ 16 mhz 22 pf r fhse internal feedback resistor between xtalin and xtalout pins 1 m r esr equivalent series resistance* v dd = 3.3 v, c l = 12 pf @ 16 mhz, hsedr = 0 160 v dd = 2.4 v, c l = 12 pf @ 16 mhz, hsedr = 1 d hse hse oscillator duty cycle 40 60 % i ddhse hse oscillator current consumption v dd = 3.3 v @ 16 mhz tbd ma i pwdhse hse oscillator power down current v dd = 3.3 v 0.01 a t suhse hse oscillator s tartup time v dd = 3.3 v 4 ms note: the following guidelines are recommended to increase the stability of the crystal circuit of the hse clock in the pcb layout : the crystal oscillator should be located as close as possible to the mcu to keep the trace length s as short as possible to reduce any parasitic capacitance. shield lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise. keep any high frequency signal lines away from the crystal area to prevent any crosstalk adverse effects .
rev. 1.21 28 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics internal clock characteristics table 12 high speed internal clock (hsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd operation range 2.0 3.6 v f hsi hsi frequency v dd = 3.3 v @ 25c 8 mhz acc hsi factory calibrated hsi oscillator frequency accuracy v dd = 3.3 v, t a = 25c -2 2 % v dd = 2.5 v ~ 3.6 v, t a = -40c ~ +85c -3 3 % v dd = 2.0 v ~ 3.6 v t a = -40c ~ +85c -4 4 % duty duty cycle f hsi = 8 mhz 35 65 % i ddhsi oscillator supply current f hsi = 8 mhz 300 500 a power down current 0.05 a t suhsi startup time f hsi = 8 mhz - 10 s table 13 low speed internal clock (lsi) characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed internal oscillator frequency (lsi) v dd = 3.3 v, t a = -40c ~ +85c 21 32 43 khz acc lsi lsi frequency accuracy after factory-trimmed, v dd = 3.3 v, t a = 25c -10 +10 % i ddlsi lsi oscillator operating current v dd = 3.3 v, t a = 25c 0.4 0.8 a t sulsi lsi oscillator s tartup time v dd = 3.3 v, t a = 25c 100 s pll characteristics table 14 pll characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll input clock 4 16 mhz f ck_pll pll output clock 16 48 mhz t lock pll lock time 200 s memory characteristics table 15 flash memory characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu number of guaranteed program/erase cycles before failure. (endurance) t a = -40c ~ +85c 10 k cycles t ret data retention time t a = -40c ~ +85c 10 years t prog word programming time t a = -40c ~ +85c 20 s t erase page erase time t a = -40c ~ +85c 2 ms t merase mass erase time t a = -40c ~ +85c 10 ms
rev. 1.21 29 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics electrical characteristics i/o port characteristics table 16 i/o port characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low level input current 3.3 v io v i = v ss , on-chip pull-up resister disabled. 3 a reset pin 3 a i ih high level input current 3.3 v io v i = v dd, on-chip pull- down resister disabled. 3 a reset pin 3 a v il low level input voltage 3.3 v io - 0.5 v dd 0.35 v reset pin - 0.5 v dd 0.35 v v ih high level input voltage 3.3 v io v dd 0.65 v dd + 0.5 v reset pin v dd 0.65 v dd + 0.5 v v hys schmitt trigger input voltage hysteresis 3.3 v io 0.12 v dd mv reset pin 0.12 v dd mv i ol low level output current (gpio sink current) 3.3 v io 4 ma drive, v ol = 0.4 v 4 ma 3.3 v io 8 ma drive, v ol = 0.4 v 8 ma 3.3 v io 12 ma drive, v ol = 0.4 v 12 ma 3.3 v io 16 ma drive, v ol = 0.4 v 16 ma i oh high level output current (gpio source current) 3.3 v i/o 4 ma drive, v oh = v dd - 0.4 v 4 ma 3.3 v i/o 8 ma drive, v oh = v dd - 0.4 v 8 ma 3.3 v i/o 12 ma drive, v oh = v dd - 0.4 v 12 ma 3.3 v i/o 16 ma drive, v oh = v dd - 0.4 v 16 ma v ol low level output voltage 3.3 v 4 ma drive io, i ol = 4 ma 0.4 v 3.3 v 8 ma drive io, i ol = 8 ma 0.4 v 3.3 v 12 ma drive io, i ol = 12 ma 0.4 v 3.3 v 16 ma drive io, i ol = 16 ma 0.4 v v oh high level output voltage 3.3 v 4 ma drive io, i oh = 4 ma v dd - 0.4 v 3.3 v 8 ma drive io, i oh = 8 ma v dd - 0.4 v 3.3 v 12 ma drive io, i oh = 12 ma v dd - 0.4 v 3.3 v 16 ma drive io, i oh = 16 ma v dd - 0.4 v r pu internal pull-up resistor 3.3 v i/o 46 k r pd internal pull-down resistor 3.3 v i/o 46 k
rev. 1.21 30 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics adc characteristics table 17 adc characteristics t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda operating voltage 2.5 3.3 3.6 v v adcin a/d converter input voltage range 0 v ref+ v v ref+ a/d converter reference voltage v dda v dda v i adc current consumption v dda = 3.3 v 1 tbd ma i adc_dn power down current consumption v dda = 3.3 v 0.1 a f adc a/d converter clock 0.7 16 mhz f s sampling rate 0.05 1 mhz t dl data latency 12.5 1/f adc cycles t s&h sampling & hold time 3.5 1/f adc cycles t adcconv a/d converter conversion time 16 1/f adc cycles r i input sampling switch resistance 1 k c i input sampling capacitance no pin/pad capacitance included 16 pf t su startup up time 1 s n resolution 12 bits inl integral non-linearity error f s = 750 khz, v dda = 3.3 v 2 5 lsb dnl differential non-linearity error f s = 750 khz, v dda = 3.3 v 1 lsb e o offset error 10 lsb e g gain error 10 lsb note: 1. guaranteed by design, not tested in production. 2. the fgure below shows the equivalent circuit of the a/d converter sample-and-hold input stage where c i is the storage capacitor, r i is the resistance of the sampling switch and r s is the output impedance of the signal source v s . normally the sampling phase duration is approximately, 3.5/f adc . the capacitance, c i , must be charged within this time frame and it must be ensured that the voltage at its terminals becomes suffciently close to v s for accu- racy. to guarantee this, r s is not allowed to have an arbitrarily large value.
rev. 1.21 31 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics electrical characteristics sar adc c i sample r i r s v s figure 7 adc sampling network model the worst case occurs when the extremities of the input range (0v and v ref ) are sampled consecutively. in this situation a sampling error below ? lsb is ensured by using the following equation: i 2n i adc s r )2 ln( cf 5.3 r ? ? ? where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where the a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, r s may be larger than the value indicated by the equation above. sctm/gptm characteristics table 18 sctm/gptm characteristics symbol parameter conditions min typ max unit f tm timer clock source for gptm 48 mhz t res timer resolution time f tm f ext external signal frequency on channel 1 ~ 4 1/2 f tm res timer resolution 16 bits
rev. 1.21 32 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics i 2 c characteristics table 19 i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min max min max min max f scl scl clock frequency 100 400 1000 khz t scl(h) scl clock high time 4.5 1.125 0.45 s t scl(l) scl clock low time 4.5 1.125 0.45 s t fall scl and sda fall time 1.3 0.34 0.135 s t rise scl and sda rise time 1.3 0.34 0.135 s t su(sda) sda data setup time 500 125 50 ns t h(sda) sda data hold time 0 0 0 ns t su(sta) start condition setup time 500 125 50 ns t h(sta) start condition hold time 0 0 0 ns t su(sto) stop condition setup time 500 125 50 ns note: 1. guaranteed by design, not tested in production. 2. to achieve 100 khz standard mode, the peripheral clock frequency must be higher than 2 mhz. 3. to achieve 400 khz fast mode, the peripheral clock frequency must be higher than 8 mhz. 4. to achieve 1 mhz fast mode plus, the peripheral clock frequency must be higher than 20 mhz. 5. the above characteristic parameters of the i 2 c bus timing are based on : seq_filter = 01 and comb_filter_en is disabled. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 8 i 2 c timing diagrams
rev. 1.21 33 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics electrical characteristics spi characteristics table 20 spi characteristics symbol parameter conditions min typ max unit spi master mode f sck spi master output sck clock frequency spi peripheral clock frequency f pclk f pclk /2 mhz t sck(h) t sck(l) sck clock high and low time t sck /2 - 2 t sck /2 + 1 ns t v(mo) data output valid time - 5 ns t h(mo) data output hold time 2 ns t su(mi) data input setup time 5 ns t h(mi) data input hold time 5 ns spi slave mode f sck spi slave input sck clock frequency spi peripheral clock frequency f pclk f pclk /3 mhz duty sck spi slave input sck clock duty cycle 30 70 % t su(sel) sel enable setup time 3 t pclk ns t h(sel) sel enable hold time 2 t pclk ns t a(so) data output access time 3 t pclk ns t dis(so) data output disable time 10 ns t v(so) data output valid time 25 ns t h(so) data output hold time 15 ns t su(si) data input setup time 5 ns t h(si) data input hold time 4 ns note: 1. f sck is spi output/input clock frequency and t sck = 1/f sck . 2. f pclk is spi peripheral clock frequency and t pclk = 1/f pclk .
rev. 1.21 34 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi ) t su(mi ) t v(mo) t h(mo) t su(mi ) t h(mi ) data valid data valid data valid data valid figure 9 spi timing diagrams C spi master mode sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 10 spi timing diagrams C spi slave mode with cpha=1
rev. 1.21 35 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 electrical characteristics package information 6 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.21 36 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 package information 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.341 bsc d 0.069 e 0.025 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.200 0.300 c 0.200 0.300 d 1.750 e 0.635 bsc f 0.100 0.250 g 0.410 1.270 h 0.100 0.250 0 8
rev. 1.21 37 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 package information package information 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.390 bsc d 0.069 e 0.025 bsc f 0.004 0.0098 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.200 0.300 c 9.900 bsc d 1.750 e 0.635 bsc f 0.100 0.250 g 0.410 1.270 h 0.100 0.250 0 8
rev. 1.21 38 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 package information saw type 33-pin (4mm4mm) qfn outline dimensions 33 symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.006 0.008 0.010 d 0.157 bsc e 0.157 bsc e 0.016 bsc d2 0.104 0.106 0.108 e2 0.104 0.106 0.108 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.700 0.750 0.800 a1 0.000 0.020 0.050 a3 0.203 bsc b 0.150 0.200 0.250 d 4.000 bsc e 4.000 bsc e 0.400 bsc d2 2.650 2.700 2.750 e2 2.650 2.700 2.750 l 0.350 0.400 0.450 k 0.200
rev. 1.21 39 of 39 april 11, 2017 32-bit arm ? cortex?-m0+ mcu HT32F52220/ht32f52230 package information package information copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw/en/home.

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